1. Field of the Invention
The present invention relates to a latch circuit that includes an input amplifying circuit that amplifies input signals and a memory logic circuit which stores data included in the input signals by using signals amplified by the input amplifying circuit, and a deserializer circuit that uses the latch circuit, and, more particularly relates to a latch circuit and a deserializer circuit which operate at high speed with low power consumption.
2. Description of the Related Art
A latch, which is a circuit that stores data, is used in various circuits such as a serializer/deserializer (SerDes) of a receiving device of a communication system of 40 gigabit per second (Gbps). FIG. 14A is a functional block diagram of a commonly used latch that is compatible with a small-amplitude input. As shown in FIG. 14A, the commonly used latch that is compatible with the small-amplitude input includes a precharging unit 110 at a first transistor level, a memory logic unit 120 at a second transistor level, an input amplifying unit 130 at a third transistor level, and a clock synchronization switch 140 at a forth transistor level. The clock synchronization switch 140 is synchronized with a clock. When clock signals are “high”, the switch is on, and when the clock signals are “low”, the switch is off.
The precharging unit 110 is a circuit that preliminarily sets voltages of nodes a and b to “high” during a first half of a clock (i.e., in a precharge time) so as to speed up data storage performed during a second half of the clock (i.e., in a latch time). Through the nodes “a” and “b”, voltages are supplied to a data storage stage. The memory logic unit 120 is a circuit that stores a voltage difference generated in accordance with the input data in the second half of the clock. The input amplifying unit 130 is a current mode logic that amplifies small-amplitude input signals and generates a voltage difference that is stored as data in the memory logic unit 120. The clock synchronization switch 140 is a switch that realizes transition between the precharge time and the latch time in synchronization with the clock. An example of the commonly used latch is indicated in J. Montanaro, R. T. Witek, K. Anne, A. J. Black, E. M. Cooper, D. W. Dobberpuhl, P. M. Donahue, J. Eno, W. Hoeppner, D. Kruckemyer, T. H. Lee, P. C. M. Lin, L. Madden, D. Murray, M. H. Pearce, S. Santhanam, K. J. Snyder, R. Stehpany, and S. C. Thierauf, “A 160-MHz, 32-b, 0.5-W CMOS RISC Microprocessor, “IEEE J. Solid-State Circuits 31, No. 11, 1703-1714(November 1996).
The commonly used latch described above, however, has a problem. The commonly used latch that is compatible with the small-amplitude input shown in FIG. 14A is configured with four levels of transistors. Therefore, a power supply voltage Vdd needs to be greater than 4Vth, which makes the level of the power supply voltage Vdd high. Here, Vth is a threshold voltage of the operation of the transistor.
In addition, As shown in FIG. 14B, a propagation delay time from an input of a clock signal CK till an output of a voltage difference V(a)−V(b) is approximately td1+2*td2, where td1 is a propagation delay time from a gate node to a source node of a metal-oxide-semiconductor field-effect transistor (MOSFET) and td2 is a propagation delay time from the source node to a drain node of the MOSFET. Normally, td1 is 30 to 50 percents of td2. Hence, the propagation delay time Tpd of the commonly used latch is expressed as Tpd=0.4×td2+2×td2=2.4td2. Therefore, a half of the clock cycle needs to be more than or equal to 2.4td2, which is a restriction on a maximum operating frequency.